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003 | RU-ToGU | ||
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007 | cr nn 008mamaa | ||
008 | 160915s2014 gw | s |||| 0|eng d | ||
020 |
_a9783319047898 _9978-3-319-04789-8 |
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024 | 7 |
_a10.1007/978-3-319-04789-8 _2doi |
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035 | _ato000542808 | ||
040 |
_aSpringer _cSpringer _dRU-ToGU |
||
050 | 4 | _aTK7888.4 | |
072 | 7 |
_aTJFC _2bicssc |
|
072 | 7 |
_aTEC008010 _2bisacsh |
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082 | 0 | 4 |
_a621.3815 _223 |
100 | 1 |
_aWilliams, John Michael. _eauthor. _9448483 |
|
245 | 1 | 0 |
_aDigital VLSI Design with Verilog _helectronic resource _bA Textbook from Silicon Valley Polytechnic Institute / _cby John Michael Williams. |
250 | _a2nd ed. 2014. | ||
260 |
_aCham : _bSpringer International Publishing : _bImprint: Springer, _c2014. |
||
300 |
_aXVI, 553 p. 273 illus., 116 illus. in color. _bonline resource. |
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336 |
_atext _btxt _2rdacontent |
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337 |
_acomputer _bc _2rdamedia |
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338 |
_aonline resource _bcr _2rdacarrier |
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505 | 0 | _aIntroductory Material -- Week 1 Class 1 -- Week 1 Class 2 -- Week 2 Class 1 -- Week 2 Class 2 -- Week 3 Class 1 -- Week 3 Class 2 -- Week 4 Class 1 -- Week 4 Class 2 -- Week 5 Class 1 -- Week 5 Class 2 -- Week 6 Class 1 -- Week 6 Class 2 -- Week 7 Class 1 -- Week 7 Class 2 -- Week 8 Class 1 -- Week 8 Class 2 -- Week 9 Class 1 -- Week 9 Class 2 -- Week 10 Class 1 -- Week 10 Class 2 -- Week 11 Class 1 -- Week 11 Class 2 -- Week 12 Class 1 -- Week 12 Class 2. | |
520 | _aThis book is structured as a step-by-step course of study along the lines of a VLSI integrated circuit design project. The entire Verilog language is presented, from the basics to everything necessary for synthesis of an entire 70,000 transistor, full-duplex serializer-deserializer, including synthesizable PLLs. The author includes everything an engineer needs for in-depth understanding of the Verilog language: Syntax, synthesis semantics, simulation, and test. Complete solutions for the 27 labs are provided in the downloadable files that accompany the book. For readers with access to appropriate electronic design tools, all solutions can be developed, simulated, and synthesized as described in the book. A partial list of design topics includes design partitioning, hierarchy decomposition, safe coding styles, back annotation, wrapper modules, concurrency, race conditions, assertion-based verification, clock synchronization, and design for test. A concluding presentation of special topics includes SystemVerilog and Verilog-AMS. Covers the entire Verilog language – using most of it in practice; Provides 27 lab exercises, with complete and tested answers; Explains and emphasizes synthesizability, wherever it pertains to language features; Develops as a major project a synthesizable 70,000-gate SerDes; Presents synthesis-relevant usage of SystemVerilog, and the basic functionality of Verilog-AMS. >. | ||
650 | 0 |
_aengineering. _9224332 |
|
650 | 0 |
_aComputer Science. _9155490 |
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650 | 0 |
_aelectronics. _9303071 |
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650 | 0 |
_aSystems engineering. _9303074 |
|
650 | 1 | 4 |
_aEngineering. _9224332 |
650 | 2 | 4 |
_aCircuits and Systems. _9303075 |
650 | 2 | 4 |
_aProcessor Architectures. _9303114 |
650 | 2 | 4 |
_aElectronics and Microelectronics, Instrumentation. _9303076 |
710 | 2 |
_aSpringerLink (Online service) _9143950 |
|
773 | 0 | _tSpringer eBooks | |
856 | 4 | 0 | _uhttp://dx.doi.org/10.1007/978-3-319-04789-8 |
912 | _aZDB-2-ENG | ||
999 | _c400181 |