000			03758nam a22004815i 4500
001			vtls000540897
003			RU-ToGU
005			20210922082053.0
007			cr nn 008mamaa
008			160915s2014 xxu| s |||| 0|eng d
020			_a9781461477983 _9978-1-4614-7798-3
024	7		_a10.1007/978-1-4614-7798-3 _2doi
035			_ato000540897
040			_aSpringer _cSpringer _dRU-ToGU
050		4	_aTK7888.4
072		7	_aTJFC _2bicssc
072		7	_aTEC008010 _2bisacsh
082	0	4	_a621.3815 _223
100	1		_aPaul, Somnath. _eauthor. _9446718
245	1	0	_aComputing with Memory for Energy-Efficient Robust Systems _helectronic resource _cby Somnath Paul, Swarup Bhunia.
260			_aNew York, NY : _bSpringer New York : _bImprint: Springer, _c2014.
300			_aXIII, 210 p. 73 illus., 41 illus. in color. _bonline resource.
336			_atext _btxt _2rdacontent
337			_acomputer _bc _2rdamedia
338			_aonline resource _bcr _2rdacarrier
505	0		_aPart I Introduction -- Challenges in Computing for Nanoscale Technologies -- A Survey of Computing Architectures -- Motivation for a Memory-Based Computing Hardware -- Part II Memory Based Computing -- Key Features of Memory-Based Computing -- Overview of Hardware and Software Architectures -- Application of Memory-Based Computing -- Part III Hardware Framework -- A Memory Based Generic Reconfigurable Framework -- MAHA Hardware Architecture -- Part IV Software Framework -- Application Analysis -- Application Mapping to MBC Hardware.
520			_aThis book analyzes energy and reliability as major challenges faced by designers of computing frameworks in the nanometer technology regime.  The authors describe the existing solutions to address these challenges and then reveal a new reconfigurable computing platform, which leverages high-density nanoscale memory for both data storage and computation to maximize the energy-efficiency and reliability. The energy and reliability benefits of this new paradigm are illustrated and the design challenges are discussed. Various hardware and software aspects of this exciting computing paradigm are described, particularly with respect to hardware-software co-designed frameworks, where the hardware unit can be reconfigured to mimic diverse application behavior.  Finally, the energy-efficiency of the paradigm described is compared with other, well-known reconfigurable computing platforms.  ·         Introduces new paradigm for hardware reconfigurable frameworks, which leverages dense memory array as a malleable resource, which can be used for information storage as well as computation; ·         Merges spatial and temporal computing to minimize interconnect overhead and achieve better scalability compared to state-of-the-art reconfigurable computing platforms; ·         Enables efficient mapping of diverse data-intensive applications from domains of signal processing, multimedia and security applications.
650		0	_aengineering. _9224332
650		0	_aComputer Science. _9155490
650		0	_aelectronics. _9303071
650		0	_aSystems engineering. _9303074
650	1	4	_aEngineering. _9224332
650	2	4	_aCircuits and Systems. _9303075
650	2	4	_aElectronics and Microelectronics, Instrumentation. _9303076
650	2	4	_aProcessor Architectures. _9303114
700	1		_aBhunia, Swarup. _eauthor. _9446719
710	2		_aSpringerLink (Online service) _9143950
773	0		_tSpringer eBooks
856	4	0	_uhttp://dx.doi.org/10.1007/978-1-4614-7798-3
912			_aZDB-2-ENG
999			_c399219