000 | 03391nam a22005055i 4500 | ||
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001 | vtls000540784 | ||
003 | RU-ToGU | ||
005 | 20210922081802.0 | ||
007 | cr nn 008mamaa | ||
008 | 160915s2014 xxu| s |||| 0|eng d | ||
020 |
_a9781461442745 _9978-1-4614-4274-5 |
||
024 | 7 |
_a10.1007/978-1-4614-4274-5 _2doi |
|
035 | _ato000540784 | ||
040 |
_aSpringer _cSpringer _dRU-ToGU |
||
050 | 4 | _aTK7888.4 | |
072 | 7 |
_aTJFC _2bicssc |
|
072 | 7 |
_aTEC008010 _2bisacsh |
|
082 | 0 | 4 |
_a621.3815 _223 |
100 | 1 |
_aTatas, Konstantinos. _eauthor. _9445154 |
|
245 | 1 | 0 |
_aDesigning 2D and 3D Network-on-Chip Architectures _helectronic resource _cby Konstantinos Tatas, Kostas Siozios, Dimitrios Soudris, Axel Jantsch. |
260 |
_aNew York, NY : _bSpringer New York : _bImprint: Springer, _c2014. |
||
300 |
_aXIII, 265 p. 144 illus., 79 illus. in color. _bonline resource. |
||
336 |
_atext _btxt _2rdacontent |
||
337 |
_acomputer _bc _2rdamedia |
||
338 |
_aonline resource _bcr _2rdacarrier |
||
505 | 0 | _aPart I: Network-on-Chip Design Methodology -- Network-on-Chip Technology: A Paradigm Shift -- NoC Modeling and Topology Exploration -- Communication Architecture -- Power and Thermal Effects and Management -- NoC-based System Integration -- NoC Verification and Testing -- The Spidergon STNoC -- Middleware Memory Management in NoC -- On Designing 3-D Platforms -- The SYSMANTIC NoC Design and Prototyping Framework -- Part II: Suggested Projects.- Projects on Network-on Chip. | |
520 | _aThis book covers key concepts in the design of 2D and 3D Network-on-Chip interconnect. It highlights design challenges and discusses fundamentals of NoC technology, including architectures, algorithms and tools. Coverage focuses on topology exploration for both 2D and 3D NoCs, routing algorithms, NoC router design, NoC-based system integration, verification and testing, and NoC reliabilty. Case studies are used to illuminate new design methodologies. · Describes essential theory, practice and state-of-the-art applications of 2D and 3D Network-on-Chip interconnect; · Enables readers to exploit parallelism in processor architecture, with interconnect design that is efficient in terms of energy and performance; · Covers topics not available in other books, such as NoC and distributed memory organization, dynamic memory management and abstract data type support in many-core platforms, and distributed hierarchical power management. | ||
650 | 0 |
_aengineering. _9224332 |
|
650 | 0 |
_aComputer Science. _9155490 |
|
650 | 0 |
_aelectronics. _9303071 |
|
650 | 0 |
_aSystems engineering. _9303074 |
|
650 | 1 | 4 |
_aEngineering. _9224332 |
650 | 2 | 4 |
_aCircuits and Systems. _9303075 |
650 | 2 | 4 |
_aElectronics and Microelectronics, Instrumentation. _9303076 |
650 | 2 | 4 |
_aProcessor Architectures. _9303114 |
700 | 1 |
_aSiozios, Kostas. _eauthor. _9445155 |
|
700 | 1 |
_aSoudris, Dimitrios. _eauthor. _9318462 |
|
700 | 1 |
_aJantsch, Axel. _eauthor. _9318640 |
|
710 | 2 |
_aSpringerLink (Online service) _9143950 |
|
773 | 0 | _tSpringer eBooks | |
856 | 4 | 0 | _uhttp://dx.doi.org/10.1007/978-1-4614-4274-5 |
912 | _aZDB-2-ENG | ||
999 | _c398295 |