| 000 | 01866nmm a22004095u 4500 | ||
|---|---|---|---|
| 001 | vtls000363094 | ||
| 003 | RU-ToGU | ||
| 005 | 20210922030129.0 | ||
| 007 | cr nn 008mamaa | ||
| 008 | 120829s2007 xx j eng d | ||
| 020 | _a9783540744429 | ||
| 035 | _ato000363094 | ||
| 040 |
_aSpringer _cSpringer _dRU-ToGU |
||
| 100 | 1 |
_aAzémard, Nadine. _9325662 |
|
| 245 | 1 | 0 |
_aIntegrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation _hЭлектронный ресурс _b17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007. Proceedings / _cedited by Nadine Azémard, Lars Svensson |
| 260 |
_aBerlin, Heidelberg : _bSpringer-Verlag Berlin Heidelberg, _c2007. |
||
| 490 | 1 | 0 |
_aLecture Notes in Computer Science, _x0302-9743 ; _v4644 |
| 650 | 0 |
_aComputer Science _9155490 |
|
| 650 | 0 |
_aComputer system performance _9303225 |
|
| 650 | 0 |
_aLogic design _9306256 |
|
| 650 | 0 |
_aMemory management (Computer science) _9306582 |
|
| 650 | 0 |
_aSystems engineering _9303074 |
|
| 650 | 1 | 4 |
_aComputer Science _9155490 |
| 650 | 2 | 4 |
_aArithmetic and Logic Structures _9307979 |
| 650 | 2 | 4 |
_aCircuits and Systems _9303075 |
| 650 | 2 | 4 |
_aLogic Design _9306256 |
| 650 | 2 | 4 |
_aMemory Structures _9306583 |
| 650 | 2 | 4 |
_aProcessor Architectures _9303114 |
| 650 | 2 | 4 |
_aSystem Performance and Evaluation _9303229 |
| 700 | 1 |
_aSvensson, Lars. _9331196 |
|
| 710 | 2 |
_aSpringerLink (Online service) _9143950 |
|
| 773 | 0 | _tSpringer e-books | |
| 830 |
_aLecture Notes in Computer Science, _9279505 |
||
| 856 | 4 | 0 | _uhttp://dx.doi.org/10.1007/978-3-540-74442-9 |
| 999 | _c241237 | ||