000 01848nmm a22004335u 4500
001 vtls000359997
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007 cr nn 008mamaa
008 120828s2005 xx j eng d
020 _a9783540320807
035 _ato000359997
040 _aSpringer
_cSpringer
_dRU-ToGU
100 1 _aPaliouras, Vassilis.
_9319963
245 1 0 _aIntegrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation (vol. # 3728)
_hЭлектронный ресурс
_b15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005, Proceedings
_cedited by Vassili
260 _aBerlin Heidelberg :
_bSpringer-Verlag GmbH.,
_c2005
490 1 0 _aLecture Notes in Computer Science,
_x0302-9743 ;
_v3728
650 0 _aComputer aided design
_9303150
650 0 _aComputer engineering
_9303142
650 0 _aComputer Science
_9155490
650 0 _aComputer science
_9155490
650 0 _aLogic design
_9306256
650 0 _aOperating systems (Computers)
_9303025
650 1 4 _aComputer Science
_9155490
650 2 4 _aArithmetic and Logic Structures
_9307979
650 2 4 _aComputer-Aided Engineering (CAD, CAE) and Design
_9303153
650 2 4 _aElectronic and Computer Engineering
_9303147
650 2 4 _aLogic Design
_9306256
650 2 4 _aPerformance and Reliability
_9566342
650 2 4 _aProcessor Architectures
_9303114
700 1 _aVerkest, Diederik
_9319964
700 1 _aVounckx, Johan
_9319965
710 2 _aSpringerLink (Online service)
_9143950
773 0 _tSpringer e-books
830 _aLecture Notes in Computer Science,
_9279505
856 4 0 _uhttp://dx.doi.org/10.1007/11556930
999 _c235425