TY  - GEN
AU  - Laputenko,Andrey V
AU  - López,Jorge
AU  - Kushik,Natalia G.
AU  - Vinarskii,Evgenii
TI  - Testing digital circuits: studying the increment of the number of states and estimating the fault coverage
KW  - конечные автоматы
KW  - тестирование цифровых схем
KW  - цмфровые схемы
KW  - статьи в сборниках
N1  - Библиогр.: 11 назв
N2  - Testing of digital circuits is very important,
especially for guaranteeing the correct and reliable
 functioning of electronic devices. One of the possibilities for
 deriving high quality test suites is using test generation
 methods for a corresponding Finite State Machine simulating
 the circuit behavior. In this paper, we estimate the number of
 implementation states whenever a circuit mutant is
 introduced. Experimental evaluation is performed for three
 types of mutants, namely Single Stuck-At Fault Mutants,
 Single Bridge Fault Mutants, and Hardly Detectable Fault
 Mutants. Experiments with the ITC’99 benchmarks (second
 release) show that in most cases the injection of a fault does
 not increase the number of states. Moreover, whenever the
 number of states is increased, the increment is on average
 20%. Given this increment, we perform the experiments to
 showcase that for testing circuits with guaranteed fault
 coverage with respect to the listed faults, one can apply the Wmethod
 with the upper bound m = 1.2n states, for n states in
 the specification (circuit) FSM
UR  - http://vital.lib.tsu.ru/vital/access/manager/Repository/vtls:000659775
ER  -